| CALL
FOR PARTICIPATION |
| |
| |
|
| Troubleshooting
how and why circuits and systems fail is important and is rapidly growing
in industry significance. Debug and diagnosis may be needed for yield
improvement, process monitoring, debugging the design function, failure
mode learning for R&D, or just getting a working first prototype.
But the detective work can become tricky. Sources of difficulty include
circuit complexity, packaging, physical access, shortened product creation
cycle, the traditional focus on just pass/fail testing, and missing tool
and equipment capabilities. New and efficient solutions for debug and
diagnosis will have a much needed and highly visible impact on productivity.
The mission and objective of the SDD06 Workshop is to consider all issues
related to debug and diagnosis of circuits and systems - from prototype
bring-up to volume production.
The topics
of interest include, but are not limited to, the following:
- Debug Techniques
and Methodologies
- Structured
Debug Architectures
- Infrastructure
IP for SDD
- Design/Synthesis
for Debug
- Microprocessor
Debug
- Debug for
FPGAs
- Reuse of DFT
for Debug and Diagnosis
- Debug of Embedded
Cores/SoCs
- Digital/analog
Turn-on
- Methods &
Tools
- System Level
Debug & Diagnosis
- Equipment Impact
and Techniques
- Manufacturing
& Prototype Environment
- Silicon Debug
Standardization
- Case Studies
|
| Advance
Program (Preliminary Version 1) |
|
Day
1 - October 26th |
|
4:15pm |
Opening
Remarks
M. Ricchetti, ATI Research, Inc., F. Muradali, National Semiconductor |
| 4:30pm -
5:45 pm |
Silicon
Debug & Diagnosis: Audience Participation |
| 6pm -
7pm |
Experience
& Opinion (Embedded Instruments: What they really look like)
- J. Rearick, Agilent
Experience
& Opinion (Debug & Diagnosis and DFM : Mutual Dependencies)
- D. Appello, STMicroelectronics
Experience
& Opinion (Tough debug & fix)
- B. Cory, nVidia
|
| Workshop
Welcome Reception - 7:00pm - 9:00pm |
Day
2 - October 27th |
| 8:15am -
9:45am |
Session
1: Chair - TBD
Experience
& Opinion (Failure Analysis)
Discussion
- What really changed from .18um down to 65nm? -
T. McLaurin, ARM
What tests
are different - or are there any? What type of reliability
is being done - or is there any? Are things really failing
differently? Are there any different mbist algorithms being used
and why? What new infrastructure was put in for debug and diagnosis
of failures? What are other considerations - what else do
we need for easier debug and diagnosis?
Panelists:
Al Crouch
- Inovys
TBD
|
| 10:15am -
12:00am |
Session
2: Chair - TBD
Paper
1 - Debug Related Standards : What’s up and What’s
Next
- N. Stollon, MIPs
Paper
2 - FPGA distributed memory to accelerate advanced process
yield learning
- J. Fan, Xilinx
Paper
3 - Behavioral Diagnosis of TDF/IRF defects for Test Learning
- C. Schuermyer, B. Benware - LSI Logic; M. Sharma,
W-T Cheng, N. Tamarapalli, H. Rahamanian - Mentor Graphics
Experience
& Opinion (Design for Debug)
- M. Abramovici, DAFCA
Experience
& Opinion (Analog turn-on)
- M. Hafed, DFT Microsystems |
| Lunch
- 12:00 pm - 1:00pm |
| 1:00pm -
2:45pm |
Session
4: Chair - TBD
Paper
4 - Serial Wire Debug & the CoreSight Debug and Trace Architecture
- P. Harrod, E. Ashfield, I. Field, S. Houlihane, W. Orme, S. Woodhouse,
ARM
Paper
5 - Dramatic Reduction in Optical Probing Tie Via Test-Loop Compaction
of ATPG Generated Test Loops
- R. Wampler, P-K Ong, R. Billings - AMD; D. Meehl -
Cadence, G. Woods, S. Kasapi - Credence
Paper
6 - Yield Improvement with Compressed Patterns Diagnosis
- I. Ahmed, J. Bartsch, S. Sharma - Skyworks; Yu Huang, W-T
Cheng, W. Yang, N. Tamarapalli - Mentor Graphics
Paper
7 - E-star: A new statistical algorithm to enhance volume diagnostic
effectiveness and accuracy
- D.
Chieppi, G. De Nicolao -Universit`a di Pavia - P. Amato, D. Appello,
K. Giarda - STMicroelectronics |
| 3:00pm -
4:45pm |
Session
5: Chair - TBD
Experience
& Opinion
- Bill Eklow, Cisco Systems
Discussion:
Needs from different products & job functions
- E-J Marinissen, NXP Semiconductor
Based on experience,
panelists will discuss what works well and what is needed (i.e.at
least 2 items/issues/tools) for successful debug and diagnosis.
The areas represented are digital, analog, test engineering and
high speed IO.
Panelists
(Tentative):
Hemang Dave
- National Semiconductor
Bart Vermeulen - NXP Semiconductor
Dan Gaudreau - ADI
Doug Josephson - Intel
Test Engineering - TBD
|
| 4:45 -
5pm |
Closing remarks |
|
| Committees |
|
| General
Chair:
M. Ricchetti - ATI Research, Inc.
Program Chair:
F. Muradali - National Semi.
Special Sessions:
B. Vermeulen - Philips
Finance:
R. Chandramouli - ARM
Local Arrangement Chair:
I. Hartanto - Xilinx
Electronic Media:
I. Bayraktaroglu - Sun
Program Committee:
M. Abramovici - DAFCA
D. Appello - STMicroelectronics
C. Boit - TU Berlin
D. Burek - Magma
W-T Cheng - Mentor Graphics
J-L Carbonero - STMicroelectronics
B. Cory - nVidia
A. Crouch - Inovys
J. Figueras - U. Barcelona
D. Gizopoulos - U. Piraeus
K. Hatayama - STARC
Y.-C. Hsu - Novas
A. Ivanov - UBC
D. Josephson - Intel
R. Kapur - Synopsys
H. Kerkhoff - U. Twente
C. Landrault - LIRMM
T. McLaurin - ARM
C. Metra - U. Bologna
R. Molyneaux - Sun Microsystems
N. Nicolici - McMaster U.
Y. Okuda - Sony
A. Orailoglu - UCSD
P. Prinetto - Poli. Di Torino
M. Renovell - LIRMM
M.S. Reorda - Poli. Di Torino
G. Roberts - McGill U.
N. Stollon - First Silicon Solutions
C. Sul - Silicon Image
J. Tyzer - U. Poznan
S. Venkataraman - Intel
B. West - Credence
H. Wienrich - National Semi.
Steering Committee:
R. Aitken - ARM
F. Muradali - National Semi.
E. J. Marinissen - Philips
M. Ricchetti - ATI (Chair)
T. W. Williams - Synopsys
Y. Zorian - Virage Logic
|
| |
|
The
3rd IEEE International Workshop on Silicon Debug and Diagnosis (SDD06)
is sponsored by the Institute of Electrical and Electronics Engineers
(IEEE) Computer Society's Test Technology Technical Council (TTTC). |
